Surface planarization is an important requirement for device reliability and depth-of-focus (DOF) requirements of advanced optical lithography tools. Depth-of-focus issues arise when attempting to focus a mask pattern on a surface area with uneven topography. The portion of the surface farther away from the imaging camera lens can be out of focus with respect to the portion of the surface closer to the imaging camera lens or vice versa. As the semiconductor technologies are scaled to sub-0.5 micron (.mu.m) dimensions, improved planarization techniques are required in order to achieve both local and global surface planarization. Local planarization involves planarization over a small portion or lateral scale of an area, while global planarization involves complete planarization over the entire chip area. To date, the following techniques have been proposed or employed for semiconductor device fabrication:
a) spin-on glass (SOG) and etch-back used for local planarization; PA1 b) spin-on resist and etch-back (REB) used for local planarization; PA1 c) in-situ planarized oxide deposition using electron cyclotron resonance, ECR, or plasma used for local planarization; PA1 d) chemical/mechanical polishing (CMP) used for global planarization; PA1 e) plasma deposited polymer films plus etch-back (e.g. that used in Lincoln Lab's work on disposable polymer films for local/global planarization); and PA1 f) phosphosilicate glass (PSG) or borophosposilicate glass (BPSG) reflow used for local planarization.
CMP is the main and until now, the only proven global planarization technique which is being seriously considered for sub-0.5 .mu.m technologies. However, successful implementations of CMP for semiconductor device manufacturing demands effective post-CMP cleaning process in order to remove the CMP-induced surface contaminants and damage. Much work remains to be done in order to make CMP a fully manufacturable and optimized process.